Analog-to-Digital Converter circuits (ADCs) are often implemented with Sigma-Delta topologies when high accuracy is required.
An example of application is in the audio field, where Sigma-Delta ADCs are the most commonly used.
As known, this topology of converters transforms an analog input signal to a digital stream of words with a low number of bits and a spectrally-shaped quantization noise.
The first Sigma-Delta converters had a single bit output (2 levels), then they evolved to multi-level outputs thanks to the usage of new design techniques.
The multi-level solution has the advantage of reducing the quantization noise at the cost of an increased complexity of the ADCs.
For this reason the output bits of these converters are mainly in the range of one (2 levels) to 5 (32 levels) and more rarely they go beyond these numbers.
FIG. 1 shows a multi-level second-order sigma-delta converter 100 of the prior art in which the shown quantizer 101 is L-levels.
The converter 100 of FIG. 1 is arranged to convert an input analog signal X into a stream of digital words Y.
The converter 100 includes a direct path d1 having a first analog integrator 102 and a second analog integrator 103 connected in series one another upstream the quantizer 101. The converter 100 further comprises a feedback path f1 arranged to subtract the digital output signal Y to the input of the first analog converter 102 and the second analog converter 103, respectively.
As known, the quantizer must not introduce delay in the direct path because the delay can cause instability, so the preferred solution to implement the quantizer is to do a flash-converter with a number of comparators equal to the output levels minus one (in this example L−1 comparators).
Other methods are possible to implement this block, but in any case low delay and a L-levels accuracy is required.
In most cases the complexity of the quantizer is the limiting factor for the increase of the number of levels.
An example of multi level sigma-delta AD converter is described in the publication “A 4 Ghz CT Sigma-Delta ADC with 70 dB and −74 dBFS THD in 125 MHz BW”, Bolatkale et al., page. 470-417, ISSCC 2011/SESSION 27/OVERSAMPLING CONVERTER IEEE International Solid-State Circuits Conference.    Document Edoardo Bonizzoni et Al: “Third-Order Siqma-Delta Modulator with 61-dB SNR and 6-MHz Bandwidth consuming 6 mW”′ ESSCIRC 2008, 34th European Solid state Circuits Conference, 1 Sep. 2008, pages 218-221, XP55020420, discloses a multi-bit third order Sigma-Delta modulator which uses a reduced number of operational amplifiers and enjoys a swing reductions at the quantizer input.    Document Aldo Pena-Perez et Al: “Double-Samplinq Analoq-look-ahead second order Sigma-Delta Modulator with reduced Dynamics”, IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS.ISCAS 2010 30 May-2 Jun. 2010-PARIS, FRANCE, IEEE, US, 30 May 2010, pages 2422-2425, XP031724395, discloses a second order Sigma-Delta modulator which ensures a reduction of the number of the quantization levels in the quantizer so that to reduce the overall power consumption of the modulator.    Document US2008/062026 A1 describes an Analog-to-Digital converter (ADC) having reduced number of quantizer output levels.